1. Field of the Invention
The present invention relates to a method of manufacturing a transistor having a structure allowing the reduction of impact ionization in a transistor formed on an SOI wafer. In particular, the present invention relates to a method of manufacturing an SOI transistor having an electric potential of a supporting substrate fixed to a GND level or a low voltage level.
2. Description of the Related Art
FIGS. 4A to 4D show a method of manufacturing a conventional SOI transistor, and FIGS. 5A and 5B are a top view and a cross-sectional view showing a structure of the conventional SO transistor. Herein, the transistor is formed by using a wafer in which a P-type semiconductor film is formed on a P-type supporting substrate through an embedded insulating film.
The conventional SOI transistor is formed in a semiconductor film 1 surrounded by a LOCOS 11 reaching an embedded insulating film as shown in FIG. 5. The transistors are completely isolated from each other by the LOCOS 11. In the case of an N-type transistor, since the semiconductor film 1 is of P-type, a transistor is formed by implanting N-type ions to source/drain regions 14 and 15.
On the other hand, in the case of a P-type transistor, the semiconductor film 1 surrounded by the LOCOS 11 is implanted with N-type ions so as to be imparted with an N-type conductivity. In this state, the source/drain regions 14 and 15 are implanted with P-type ions to form a transistor.
As a manufacturing method, as shown in FIGS. 4A to 4D, first, a nitride film 8 is grown. The formed nitride film 8 is patterned and then is thermally oxidized to form the LOCOS 11. The nitride film 8 is oxidized so that the LOCOS 11 has a thickness reaching the embedded insulating film 2. Next, ion implantation is conducted by using a resist 6 as a mask so as to form a well 7 (FIG. 4A). At this point, an energy of the ion implantation is controlled so as to have a density peak in the semiconductor film.
Next, a thermal treatment is conducted so as to activate and diffuse the implanted ions. After formation of the LOCOS 11, the formation of a gate oxide film 13, the formation of a gate electrode 12, and the ion implantation to the source/drain regions 14 and 15 of the transistor are performed. Then, an interlayer insulating film 18 is formed (FIG. 4C). Furthermore, the interlayer insulating film 18 is patterned and etched to form contacts 19 to the gate electrode 12 and the source/drain regions 14 and 15. Then, a wiring 20 is provided (FIG. 4D).
Since an electric potential of the supporting substrate 3 affects the characteristics of the transistor in the case of the SOI transistor, it is necessary to fix the electric potential of the supporting substrate 3. Therefore, the electric potential of the supporting substrate 3 is obtained from an electrically conductive pedestal adhered through an electrically conductive adhesive when the supporting substrate is to be mounted onto a package. Normally, the supporting substrate 3 is connected to a ground terminal or a power source voltage terminal.
In a conventional method of forming an SOI transistor, since the transistor formed on the semiconductor film and the supporting substrate are not electrically connected to each other because of the presence of the embedded insulating film between the supporting substrate and the semiconductor film, an electric potential of the supporting substrate is in a floating state. In the case of a fully depleted SOI transistor or the like, however, the semiconductor film is entirely depleted in its thickness direction to such a degree that the depletion reaches the embedded insulating film. Therefore, the characteristics of the transistor are greatly affected by the electric potential of the supporting substrate. As a result, a variation in the electric potential of the supporting substrate exhibits similar characteristics as the back gate effect of a bulk transistor.
Thus, it is necessary to fix the electric potential of the supporting substrate. A method of fixing the electric potential of the supporting substrate is normally conducted by adhering the supporting substrate to an electrically conducive pedestal through an electrically conductive adhesive upon mounting on a package. In this state, the electric potential of the pedestal is fixed so as to fix the electric potential of the supporting substrate. The electric potential of the supporting substrate is connected either to a ground terminal or to a power source voltage terminal. In order to fix the electric potential of the supporting substrate, there is also a method of providing a through hole penetrating through the semiconductor film and the embedded insulating film to reach a part of the supporting substrate.
In the case where the electric potential of the supporting substrate is fixed by the above-described connection methods, a parasitic transistor using the supporting substrate as a gate is formed. When the electric potential of the supporting substrate serving as the gate of the parasitic transistor is set to the GND level, a difference in the electric potential between the gate and a drain is increased. As a result, impact ionization occurs in the proximity of the drain of a body.
Unlike the SOI transistor, a parasitic transistor is not formed in a conventional bulk transistor. Therefore, although the impact ionization occurs in a concentrated manner only in the vicinity of the substrate surface in the proximity of a drain in the conventional bulk transistor, the impact ionization occurs even in the vicinity of the embedded insulating film in the proximity of the drain in addition to the vicinity of the substrate surface in the proximity of the drain in the SIO transistor due to formation of a parasitic transistor. The amount of generated impact ions is increased, so that a parasitic bipolar phenomenon, in which a hole of a pair of an electron and a hole flows into a source as a bipolar current, is likely to occur in an N-type transistor. As a result, the operation of the transistor cannot be controlled by a gate voltage.
As a method of restraining the occurrence of the parasitic bipolar phenomenon, there is a method of setting a body electric potential as shown in FIG. 6 so as to compulsively pull holes out from a body. However, since a layout of the transistor used for a bulk transistor is remarkably different from that used for the SOI transistor, a layout modification from a conventional layout becomes a great encumbrance in the case where a circuit design using the SOI device is to be achieved. Furthermore, in principle, the SOI device has a latchup free structure. Therefore, it is not necessary to provide a guard ring for the transistor, and thus is greatly effective to reduce the area. In the method of setting a body electric potential so as to compulsively pull the holes out from the body, however, the effects of the SOI device of reducing the area is disadvantageously halved.